The present invention relates to repeater cells in very large scale integration (VLSI) circuits, and in particular to the optimum placement and routing to and from such repeater cells.
In today's high frequency VLSI chips, delays through both active gates and wires have become equally important in determining the total critical path delay. As process technology and supply voltage are scaled, the active gate delay comes down quickly. The gate delay can fall into the sub nano-second range easily with today's advanced processes and scaled supply voltages. On the other hand, wire delay does not scale well due to the increased coupling capacitance and the increased series resistance in finer wires.
The use of repeaters or buffers in long wires can alleviate this delay problem. The RC time constant of a long wire follows the square rule with its length. Doubling the wire length quadruples the delay time at the end of the wire. On the other hand, the delay is only doubled when compared to the original wire delay (plus any added repeater gate delay) with the insertion of a repeater at the mid-point. This is an improvement in delay time when compared to the case without the use of repeaters.
Repeaters have been commonly used in high frequency chip design to resolve the long wire delay problem. The procedure can be described as follows: with an existing routed chip, all long signal wires are analyzed and identified for critical nets. This can be done using a SPICE program to simulate the signal net with the proper lumped or distributed RC model. Once repeater placement is identified, they can be inserted in the signal line where they are needed. The repeater cell can reside in a standard cell block, in a data path block, or in a stand-alone repeater block. However, they all occupy extra spaces in the layout.
In a high frequency VLSI chip running above 500 Mhz the required number of repeaters is quite significant. It was estimated that more than 15,000 repeaters are needed for a chip with die size of 18 mm.times.18 mm, compared to a few hundred for a 200 MHz or less chip. Also, the estimated wire distance between each repeater is about 4 mm.
The repeaters are essentially dedicated buffers which can be located at different positions on the chip. When a repeater is needed, the wire position where it is needed is broken and routed to the repeater and back. Depending on how close the repeater block happens to be, this additional wire routing can add additional delays.